6.8
If a bump is observed after the pulse at high powers (particularly after long pulses), look at
the V
CC
line. If this has a corresponding bump, then:
a) The regulator is inadequate; or
b) The voltage desensitizer is incorrectly set; or
c) The V
CC
power traces are not wide enough.
Try increasing the decoupling capacitor, put a larger decoupling cap right on pin 7, or test to see if
a cap on outlying parts of V
CC
(e.g. where the A2 or A3 DC trims connect to V
CC
) solves the
problem.
6.9
We have sometimes noticed small perturbations of the pulse wave- form at very low input
power (high gain), which we have traced to a coupling effect of the package lid. This lid is not
grounded as supplied. Any such effect is very small, and in any case can be easily eliminated. If
you think you see such an effect, a test is easily made by temporarily grounding the lid. A
permanent ground may be easily made, if needed, by soldering a very small wire to the lid.
6.10
As mentioned previously (in section 2.4), the S+ and S- summing junctions are high-
impedance nodes, and care should be taken not to load them capacitively. A major effect of such
loading is to slow down the output rise time. Various speedup suggestions are described in
section 10.1, item 4. In general, the fastest possible output- stage rise time, whether or not S+
and S- have been pinned out, will be obtained when the output gain is kept low (25 mV/dB or
less), and the output load is also kept low (or an external drive transistor is used). If both the
fastest possible rise time and a high transfer slope are needed, an external buffer amplifier should
be utilized.
ANADYNE is presently implementing several major improvements for the L-17C. Among these
improvements are reduced sensitivity of the S+ and S- junctions to capacitive loading, and an
even faster overall rise time.
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