Stage II can be very simply accomplished by selecting the appropriate value of R17, as described
in sub-section 8.3.6 above. In the event that this level of compensation (which should be within
0.5dBm over the -55
0
C to +85
0
C range) is insufficient, the net RT3, S2, and RT4 is used to
provide a compensating offset to the positive input of the output amplifier. To select the required
values of RT3 and RT4, a look-up table is constructed from measurements made (at room temp.)
as described in sub-section 8.3.1. Data from the same transfer curves run for Stage I are then
used to set the compensation for the high-power region of the transfer curves, as described in
sub-section 8.3.2. As in Stage I, these same values of RT3 and RT4 should work for succeeding
units of the same configuration.
Stage III consists of the selection of the required value of RT2 (or in rare instances RT1), using the
low-power data from the same set of transfer curves used for Stages I and II. RT2 causes a
temperature- dependent offset of A2, and is selected to effectively compensate any temperature-
dependent shift which is observed at the low-power end of the transfer curve. The selection
procedure is very simple, and is detailed in sub-section 8.3.3 (or 8.3.4, if RT1 is used instead).
As succeeding units of the same configuration are built and tested, it will be observed that little or
no change in the values of the temperature-compensating components is required, especially for
Stages I and II. The degree to which the required value of RT2 (the usual Stage III compensation
component) varies from unit to unit depends in large measure on where the start of logging is set,
since this determines the overall gain at low power. Even if the logging range of interest starts at a
rather low power, in most cases just two measurements, for instance at the hot temperature and at
room temperature, will suffice to allow the selection of RT2.
8.3.8
Wafer-to-Wafer Variation:
One factor which could affect the usual unit-to-unit
reproducibility of the optimum values of the temperature-compensating components arises from
the possible wafer- to-wafer variation of certain key substrate device parameters. This could in
principle be seen when units are fabricated using ICs from different wafers. If such an effect were
observed, this would require running a new set of transfer measurements over temperature to re-
define the optimum values of at least some of the temperature- compensating components. Since
each wafer normally contains over 600 good ICs, this would not be a frequent concern in
production.
To date, ANADYNE has not observed any significant effects of this nature after examination of
several wafers. In any case, there are stringent limits on the allowable variation in substrate
device parameters. These parameters are carefully reviewed by ANADYNE for each wafer.
Wafers are normally supplied to ANADYNE in batches of five, which are fabricated at
approximately the same time. We are informed by the foundry that such five-wafer batches
usually exhibit very similar device parameter spreads. However, we will nevertheless make a
practice of notifying each customer when supplying ICs from a different wafer.
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