On almost all the IC packages we have received to date, the 7-digit code on the top surface of the
IC package is placed above the orientation dot on the bottom surface, and hence also ends up on
the "C" side of the "L17C" square on the board.
2. Three jumper cables are required, as indicated on the board itself: two on the V
cc
line, and one
on the A1 output line.
3. We have found several errors in the labeling of the actual PC board, all of which have been
corrected in the board layout figures in the application notes. The first problem pertains to the
location on the board of the components S2, RT3, and RT4. Figs. 10(i), 10(j), and 10(k) show how
these components should be positioned for correct loading. These figures also show where two
new holes have been drilled in the actual board to accommodate the connection between RT3 and
S2. It is essential to scrape or cut away the ground plane surrounding these two new holes, so
that RT3 and S2 do not short to ground at this point.
The keen observer will note that the actual board has two "C5" component labels. The one
located to the right of the outlined box marked "A1 IN -" should have been labeled "C5A", and is so
labeled in Figs. 10(i), 10(j), and 10(k).
This same observer will no doubt additionally note that the actual board also has two "C12"
component labels. The one located just below the "CVP" label which is at the lower left of the
center "L17C" box should have been labeled "C10", and is so labeled in Figs. 10(i), 10(j), and
10(k).
Further, on the actual PC board the indicated decoupling cap for pin 14 (V
EE3
, at the upper-left-
hand corner of the IC) is erroneously labeled CVP instead of CVM. In any case, it is not
necessary to decouple at pin 14, as this V
EE
pin is directly connected to pin 22 (V
EE2
), both
internally (in the IC) and on the PC board. This CVP label has accordingly been crossed out in
Figs. 10(i), 10(j), and 10(k).
Finally, the location of RT2 (see Fig. 2(b)) is not labeled on the board. RT2 uses the holes next to
RR5A (on the side opposite RR4A), near the lower-right-hand corner of the board. Its location is
indicated in Figs. 10(i), 10(j), and 10(k).
4. As mentioned previously, ICs with S+ and S- pinned out (pinout #40) show a slower rise time
than those in which they are not pinned out. When using ICs with S+ and S- pinned out on the
PC36-1 board, we find that the rise time is about 14 nanoseconds. Although a rise time of 12
nanoseconds (or a little less) can be achieved by the use of positive feedback on the output
amplifier (1 pF cap in series with a 239 ohm resistor between pins 18 and 21), it is better to use
the pinout #41 version with an external summing amp if a very fast rise time is needed in a dual-
DLVA configuration.
We have also found when using the PC36-1 board that the rise time can be speeded up
somewhat by cutting the trace leading to C14. This is clearly a capacitive loading effect, and leads
to a rise time speedup of about 1 nanosecond when using the pinout #41 (no S+S-) package.
However, as a result of the board layout, cutting this trace also cuts the path to R16, which is the
output DC trim adjustment. This may not matter for test purposes. Of course, R16 can be
connected directly from pin 20 to V
CC
or to ground, as required.
-37-
 |
 |
 |
 |
 |