L-17C USERS NEWS NOTE
March 24, 1992
(This News Note also incorporates any and all prior L-17C updates subsequent to Rev. 5 of the
Application Notes) (dated Sept. 12, 1990)
A: Circuit Improvements to the L-17C Log Video IC
Several circuit improvements have recently been incorporated into the L-17C. All the pin functions remain
the same, and to the best of our knowledge, none of the circuit alterations will adversely affect any current
applications. All L-17Cs purchased from ANADYNE since July 26, 1991, whether packaged or unpackaged,
include these improvements. In brief, the principal advantages of the modified circuit are:
1.
Faster rise time (to about 5 ns) is now possible.
2.
Simpler external circuitry (and lower current draw) for negative and bipolar output.
3.
Decreased sensitivity of the summing junctions (pins 8 and 15) to external capacitive loading.
4.
Decreased sensitivity to electrostatic discharge.
5.
Simplified temperature compensation for many applications.
Below is a brief description of each circuit modification.
The normal currents for all the log stages have been increased from 100 microamps to 200 microamps in
the modified design; also, the 2k internal resistors connecting pins 8 and 15 to VCC have been changed to
1k. The purpose of these changes is to speed up the combined log stage-output stage rise time, especially
at the higher output stage gains (high transfer slopes), and also to decrease the slowing effect of pinning out
and using the summing junctions (pins 8 and 15). The sensitivity of these summing junctions to capacitive
loading has been reduced by a factor of two. Rise times as fast as 5 ns can now be attained with packaged
L-17Cs (pinout #41). The speed of the pinout #40 version will also be significantly increased.
For applications requiring low bandwidth-associated noise, the higher speed of the new L-17C design might
be undesirable. In such cases, slowing the output can be easily accomplished by using, e.g., a small
capacitor (C16) between pins 19 and 20 (see in the app. notes Fig. 2(c), and also the last paragraph and
note 4 on page 9). If speed-up components have been used in an existing design, the higher speed of the
new L-17C may result in pulse overshoots or oscillations. These can readily be eliminated by removing the
speed-up components, and/or slowing the circuit as described above and in the application notes. The
application notes (Rev. 5, September 12, 1990) should be modified for the new version of the L-17C as
follows: In Appendix B, Fig. B4,
1.
Change the 100
A log-stage currents shown to 200
A.
2.
Change the values of the internal resistors which connect pins 8 and 15 to 6 volts from 2k to 1k.
Also, in Appendix D:
Page D1, para. 5, line 9 - change ~600 mV to ~500 mV. (This is not associated with the new design
changes, but we have observed typical
numbers of 470 mV to 500 mV in ICs from recent L-17C
wafers. There is, however, no significant effect on applications.)
Page D3, para. 2, line 1 - change "100 microamps per stage" to "200 microamps per stage"; line 2 -
change "200 microamps total current" to "400 microamps total current"; line 3 - change ~4000 ohms
to ~2000 ohms.
 |
 |
 |
 |
 |