APPLICATION NOTES FOR THE ANADYNE, INC. L-17D© LOGARITHMIC VIDEO AMPLIFIER 1. INTRODUCTION |
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| ANADYNE's purpose in designing this IC was to develop a DC-coupled LVA which would greatly facilitate the production of detector log video amplifiers (DLVAs) which easily meet or exceed present program performance specifications. Particular attention was paid to the incorporation of features which enable rapid and inexpensive assembly and tuning in a production environment. In addition, we wished to anticipate likely future requirements by achieving greatly-decreased power usage, substantial size reduction, greatly improved long-term reliability, and significantly lower noise than existing DLVAs. | |||||
| Both the linearity and the gain and drift stability of the L-17D are excellent (tunable to within ±0.3 and ± 0.5 dB respectively) over the full military temperature range, as is its performance at very high duty-cycle. A recovery time of <100 nS (to within ± 1 dB) has been readily achieved at the high-power end of a 45-dBm dynamic range, using simple recovery nets. Recovery is faster at lower powers. L-17D recovery times of <50 nS (for the IC without a detector) have been achieved with a linear input over a 40-dB (power) dynamic range. Note this is the recovery time for the chip from maximum output. i.e. where A1 limits. For a linear input the range is less than it is with a detector, as detectors tend to compress the input signal at higher powers.Quiescent power is about 375 mW at ± 6 volts. Rise times of less than 6 nanoseconds are practical in appropriate layouts, with a transit time of <9 nS. The amplifier is very quiet, with a typical TSS of less than -45 dBm at 20 MHz video bandwidth, including the noise contribution of a tunnel diode detector (K = 700). The rms noise figure of the L-17D itself is about 1.2 nV/Hz1/2 at 25oC. The body size of the standard 36-pin IC package is about 10mm x 10mm. | |||||
| These application notes were prepared principally for new users of the L-17D. In general, they refer primarily to the normal 36-pin package configuration of the IC, as used in the ANADYNE-designed test and evaluation PC board (designated the PC17D). The purpose of this PC board is to expedite the process of hands-on familiarization with the L-17D's performance characteristics and versatility. This experience will also facilitate the subsequent design of miniaturized PC boards using chip components, or the design of hybrid structures for the user's specific applications. The general internal architecture and functional pinout of the IC is presented in Fig. 1(a), and the normal package pinout diagram is shown in Fig. 1(b). | |||||
| The L-17D was designed for a wide variety of applications. As a consequence, the ancillary circuitry for the PC17D test board may appear complex at first sight, with a relatively large number of components labeled as "FS" (factory select). However, it will never be necessary to use all these components in any given application. Many, in fact, are intended to produce competing effects, such as "speedup" or "slowdown" of one or another of the amplifiers internal to the IC. Furthermore, once the optimum external circuitry for a given application and layout has been specified, almost all the components can be preselected for subsequent units of the same type. | |||||
3 February 20, 2008 |
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